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Sercos III Stack
All of the functionality required to configure a Sercos III interface is contained in a stack that is available in both “hard” and "soft" versions.
The hard version is widely used for embedded applications (such as drives, I/O modules and micro-controller based motion control), where:
- It is important that the overhead of managing the Sercos III nodes not be placed upon the device processor.
- Nanosecond jitter is required.
The hardware stack is available in a number of different forms. These currently include:
- A bit stream for Xilinx FPGAs
- A bit stream for Altera FPGAs
- A Net list for Xilinx FPGAs
- A Net list for Altera FPGAs
- The "netX" multi-network controller chip
from Hilscher, GmbH
The maximum jitter allowed with hard-stack-based masters
and slaves is smaller than 1 µsec. Using the above
stacks yields a jitter similar to Sercos II (35-70
nanoseconds).
Sercos III also supports a "soft master",
using a completely software-based stack for the master
interface. Since the maximum jitter in such a
configuration is dependent upon the operating system of
the master, the maximum jitter may be set by a variable
for the Sercos III network when a soft master is
employed.
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